VIPackTM, a sophisticated packaging platform designed to provide vertically integrated package solutions, was introduced by Advanced Semiconductor Engineering, Inc. (ASE), a subsidiary of ASE Technology Holding Co., Ltd. VIPackTM is the next iteration of ASE's 3D heterogeneous integration architecture, which expands design principles while achieving ultra-high density and performance. To assist companies achieve unparalleled innovation when integrating numerous chips into a single package, the platform uses advanced redistribution layer (RDL) procedures, embedded integration, and 2.5D and 3D technologies.
The semiconductor market is growing at an exponential rate as our world moves into the data-centric era, with growth coming from devices used in artificial intelligence (AI), machine learning (ML), 5G communications, high performance computing (HPC), internet-of-things (IoT), and automotive applications. There has never been a greater demand for novel package and IC co-design, cutting-edge wafer-level fabrication techniques, complex packaging technologies, and comprehensive product and testing solutions.
As applications demand solutions that offer higher performance, greater functionality, and increased power while meeting rigorous cost limitations, packaging has become increasingly important. Demand for multi-chip integration into a single package is increasing as chiplet-based co-designs become more popular. In environments where 3D heterogeneous integration is vital, VIPackTM creates a collaborative platform for excellent interconnect solutions.
VIPackTM is ASE's packaging technology platform, which is supported by a full and integrated co-design environment. These include ASE's RDL-based high-density Fanout Package-on-Package (FOPoP), Fanout Chip-on-Substrate (FOCoS), Fanout Chip-on-Substrate-Bridge (FOCoS-Bridge), and Fanout System-in-Package (FOSiP), as well as TSV-based 2.5D and 3D IC and Co-Packaged Optics processing capabilities. The VIPackTM platform enables groundbreaking, highly integrated silicon packaging solutions that optimize clock speed, bandwidth, and power delivery while reducing co-design time, product development time, and time to market.
Critical new innovations such as double-sided RDL have allowed a series of new vertically integrated package technology pillars that create the backbone of our VIPack™ platform.”
Mark Gerber, Sr. Director of Technical Marketing and Promotion at ASE.
The VIPackTM platform enables dense horizontal and vertical interconnect solutions for disaggregated SoCs and HBM (High Bandwidth Memory) used in cutting-edge HPC, AI, ML, and network applications. High-speed networking is additionally hampered by multiple complicated optical packaging components that necessitate VIPackTM innovation to bring these components together in a vertical structure for both space and performance. VIPackTM supports mobile applications with ultra-low profile SIP modules that solve the common RF iterative design process and offer a greater degree of performance with integrated passives in the RDL layers. Also, the next generation of application processors takes into account the need for lower-profile packaging options and addresses concerns about power delivery in advanced silicon nodes.